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Publications

Selected publications

  1. Design of 50-nm Vertical MOSFET Incorporating a Dielectric Pocket (Journal article - 2004)
  2. Reduction of parasitic capacitance in vertical mosfets by spacer local oxidation (Journal article - 2003)
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2019

2017

Biomedical diagnostics enabled by integrated organic and printed electronics

Ahmadraji, T., Gonzalez-Macia, L., Ritvonen, T., Willert, A., Tuurala, S., Donaghy, D., . . . Killard, A. (2017). Biomedical diagnostics enabled by integrated organic and printed electronics. Analytical Chemistry, 89(14), 7447-7454. doi:10.1021/acs.analchem.7b01012

DOI
10.1021/acs.analchem.7b01012
Journal article

2015

Design Of A High Gain Organic Comparator For Use In Low-Cost Smart Sensor Systems

Wanjau, R. W., Donaghy, D., & Raja, M. (2015). Design Of A High Gain Organic Comparator For Use In Low-Cost Smart Sensor Systems. In 2015 11TH CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME) (pp. 37-40). Retrieved from https://www.webofscience.com/

Conference Paper

2012

Impact of universal mobility law on polycrystalline organic thin-film transistors

Raja, M., Donaghy, D., Myers, R., & Eccleston, B. (2012). Impact of universal mobility law on polycrystalline organic thin-film transistors. Journal of Applied Physics, 112(8). doi:10.1063/1.4758182

DOI
10.1063/1.4758182
Journal article

2011

IMPACT OF THE UNIVERSAL MOBILITY LAW ON POLYCRYSTALLINE ORGANIC DEVICE AND CIRCUIT OPERATION

RAJA, M., MYERS, R., DONAGHY, D., & ECCLESTON, W. (2011). IMPACT OF THE UNIVERSAL MOBILITY LAW ON POLYCRYSTALLINE ORGANIC DEVICE AND CIRCUIT OPERATION. International Journal of High Speed Electronics and Systems, 20(04), 853-866. doi:10.1142/s0129156411007100

DOI
10.1142/s0129156411007100
Journal article

A study on the importance of isolation of the active regions for high performance organic circuits

Myers, R., Donaghy, D., & Raja, M. (2011). A study on the importance of isolation of the active regions for high performance organic circuits. MRS Proceedings, 1359. doi:10.1557/opl.2011.752

DOI
10.1557/opl.2011.752
Journal article

Modeling of Polycrystalline Organic Thin-Film Transistor and Schottky Diode for the Design of Simple Functional Blocks

Raja, M., Donaghy, D., Myers, R., & Eccleston, W. (2011). Modeling of Polycrystalline Organic Thin-Film Transistor and Schottky Diode for the Design of Simple Functional Blocks. MRS Proceedings, 1359. doi:10.1557/opl.2011.753

DOI
10.1557/opl.2011.753
Journal article

2006

Experimental observation of the density of localized trapping levels in organic semiconductors

Sedghi, N., Donaghy, D., Raja, M., Badriya, S., Higgins, S. J., & Eccleston, W. (2006). Experimental observation of the density of localized trapping levels in organic semiconductors. Journal of Non-Crystalline Solids, 352(9-20), 1641-1643. doi:10.1016/j.jnoncrysol.2005.10.049

DOI
10.1016/j.jnoncrysol.2005.10.049
Journal article

Variable temperature capacitance-voltage measurements to investigate the density of localized trapping levels in organic semiconductors

Sedghi, N., Donaghy, D., Raja, M., Badriya, S., Higgins, S. J., & Eccleston, W. (2006). Variable temperature capacitance-voltage measurements to investigate the density of localized trapping levels in organic semiconductors. Material Research Society (MRS) proceedings, 905E. Retrieved from http://journals.cambridge.org/action/displayJournal?jid=OPL

Journal article

2005

Variable Temperature Capacitance-Voltage Measurements to Investigate the Density of Localized Trapping Levels in Organic Semiconductors

Sedghi, N., Donaghy, D., Raja, M., Badriya, S., Higgins, S. J., & Eccleston, B. (2005). Variable Temperature Capacitance-Voltage Measurements to Investigate the Density of Localized Trapping Levels in Organic Semiconductors. MRS Proceedings, 905. doi:10.1557/proc-0905-dd06-02

DOI
10.1557/proc-0905-dd06-02
Journal article

2004

Practicability of the development of design tools for polymer TFT circuit development

Raja, M., Sedghi, N., Donaghy, D., Lloyd, G., Badriya, S., Higgins, S. J., & Eccleston, B. (2004). Practicability of the development of design tools for polymer TFT circuit development. SPIE Proceedings, 5464, 382. doi:10.1117/12.547722

DOI
10.1117/12.547722
Journal article

Recent developments in deca-nanometer vertical MOSFETs

Hall, S., Donaghy, D., Buiu, O., Gili, E., Uchino, T., Kunz, V. D., . . . Ashburn, P. (2004). Recent developments in deca-nanometer vertical MOSFETs. Microelectronic Engineering, 72(1-4), 230-235. doi:10.1016/j.mee.2003.12.042

DOI
10.1016/j.mee.2003.12.042
Journal article

Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance

Gili, E., Kunz, V. D., de Groot, C. H., Uchino, T., Ashburn, P., Donaghy, D. C., . . . Hemment, P. L. F. (2004). Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance. Solid-State Electronics, 48(4), 511-519. doi:10.1016/j.sse.2003.09.019

DOI
10.1016/j.sse.2003.09.019
Journal article

Design of 50-nm Vertical MOSFET Incorporating a Dielectric Pocket

Donaghy, D., Hall, S., deGroot, C. H., Kunz, V. D., & Ashburn, P. (2004). Design of 50-nm Vertical MOSFET Incorporating a Dielectric Pocket. IEEE Transactions on Electron Devices, 51(1), 158-160. doi:10.1109/ted.2003.821378

DOI
10.1109/ted.2003.821378
Journal article

Practicability of the development of design tools for polymer TFT circuit development

Raja, M., Sedghi, N., Donaghy, D., Lloyd, G. R. C., Badriya, S., Higgins, S. J., & Eccleston, W. (2004). Practicability of the development of design tools for polymer TFT circuit development. SPIE proceedings, 5464, 382.

Journal article

2003

Reduction of parasitic capacitance in vertical mosfets by spacer local oxidation

Kunz, V. D., Uchino, T., de Groot, C. H., Ashburn, P., Donaghy, D. C., Hall, S., . . . Hemment, P. L. F. (2003). Reduction of parasitic capacitance in vertical mosfets by spacer local oxidation. IEEE Transactions on Electron Devices, 50(6), 1487-1493. doi:10.1109/ted.2003.813334

DOI
10.1109/ted.2003.813334
Journal article

2002

Investigating 50nm Channel Length Vertical MOSFET Containing a Dielectric Pocket, in a Circuit Environment

Donaghy, D. C., Hall, S., Kunz, D., de Groot, K., & Ashburn, P. (2002). Investigating 50nm Channel Length Vertical MOSFET Containing a Dielectric Pocket, in a Circuit Environment. In 32nd European Solid-State Device Research Conference (pp. 499-502). IEEE. doi:10.1109/essderc.2002.194977

DOI
10.1109/essderc.2002.194977
Conference Paper

2001

A simulation study to quantify the advantages of silicon-on-insulator (SOI) technology for low power

Donaghy, D., Brackenbury, L., & Hall, S. (2001). A simulation study to quantify the advantages of silicon-on-insulator (SOI) technology for low power. In IEE Colloquium (Digest) (pp. 69-74).

Conference Paper