2023
PCB Hardware Trojan Run-Time Detection Through Machine Learning. (Journal article)
Piliposyan, G., & Khursheed, S. (2023). PCB Hardware Trojan Run-Time Detection Through Machine Learning.. IEEE Trans. Computers, 72, 1958-1970.
2022
Piliposyan, G., & Khursheed, S. -S. (2022). PCB Hardware Trojan Run-time Detection Through Machine Learning. IEEE Transactions on Computers.
Yousuf, S., Khan, S., & Khursheed, S. -S. (2022). Remaining Useful Life (RUL) Regression Using Long-Short Term Memory (LSTM) Networks. Microelectronics Reliability. doi:10.1016/j.microrel.2022.114772DOI: 10.1016/j.microrel.2022.114772
Piliposyan, G., & Khursheed, S. (2022). Computer Vision for Hardware Trojan Detection on a PCB Using Siamese Neural Network. In 2022 IEEE PHYSICAL ASSURANCE AND INSPECTION OF ELECTRONICS (PAINE) (pp. 15-21). doi:10.1109/PAINE56030.2022.10014967DOI: 10.1109/PAINE56030.2022.10014967
Narwariya, A. S., Das, P., Khursheed, S., & Acharyya, A. (2022). Operational Age Estimation of ICs using Gaussian Process Regression. In 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE. doi:10.1109/dft56152.2022.9962355DOI: 10.1109/dft56152.2022.9962355
Martinez, A. L. H., Khursheed, S., Alnuayri, T., & Rossi, D. (2022). Online Remaining Useful Lifetime Prediction Using Support Vector Regression. IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, 10(3), 1546-1557. doi:10.1109/TETC.2021.3106252DOI: 10.1109/TETC.2021.3106252
Piliposyan, G., Khursheed, S., & Rossi, D. (2022). Hardware Trojan Detection on a PCB Through Differential Power Monitoring. IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, 10(2), 740-751. doi:10.1109/TETC.2020.3035521DOI: 10.1109/TETC.2020.3035521
Piliposyan, G., Khursheed, S., & Rossi, D. (2022). Hardware Trojan Detection on a PCB Through Differential Power Monitoring.. IEEE Trans. Emerg. Top. Comput., 10, 740-751.
2021
Alnuayri, T., Martinez, A. L. H., Khursheed, S., & Rossi, D. (2021). A Support Vector Regression based Machine Learning method for on-chip Aging Estimation. In 2021 4th International Conference on Computing & Information Sciences (ICCIS). IEEE. doi:10.1109/iccis54243.2021.9676376DOI: 10.1109/iccis54243.2021.9676376
Narang, A., Venu, B., Khursheed, S. -S., & Harrod, P. (2021). An Exploration of Microprocessor Self-Test Optimisation Based On Safe Faults. In 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.
Alnuayri, T., Khursheed, S. -S., Hernández Martínez, A. L., & Rossi, D. (2021). Differential Aging Sensor using Sub-threshold Leakage Current to Detect Recycled ICs. IEEE Transactions on Very Large Scale Integration Systems.
Kalanadhabhatta, S., Dutt, R., Khursheed, S., Acharyya, A., & IEEE. (2021). IC age estimation methodology using IO pad protection diodes for prevention of Recycled ICs. In 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). doi:10.1109/ISCAS51556.2021.9401363DOI: 10.1109/ISCAS51556.2021.9401363
Alnuayri, T., Khursheed, S., Martinez, A. L. H., & Rossi, D. (2021). Differential Aging Sensor to Detect Recycled ICs using Sub-threshold Leakage Current. In PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021) (pp. 1500-1503). doi:10.23919/DATE51398.2021.9473975DOI: 10.23919/DATE51398.2021.9473975
2020
Reddy, R. P., Acharyya, A., & Khursheed, S. (2020). A Cost-Aware Framework for Lifetime Reliability of TSV-Based 3D-IC Design. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 67(11), 2677-2681. doi:10.1109/TCSII.2020.2970724DOI: 10.1109/tcsii.2020.2970724
Kalanadhabhatta, S., Anumandla, K. K., Khursheed, S., & Acharyya, A. (2020). Secure Scan Design with a Novel Methodology of Scan Camouflaging. In 24TH IEEE EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD 2020). Retrieved from https://www.webofscience.com/
Martinez, A. L. H., Khursheed, S., & Rossi, D. (2020). Leveraging CMOS Aging for Efficient Microelectronics Design. In 2020 26TH IEEE INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2020). doi:10.1109/iolts50870.2020.9159742DOI: 10.1109/iolts50870.2020.9159742
Martínez, L. H., Khursheed, S., & Reddy, S. M. (2020). LFSR generation for high test coverage and low hardware overhead. IET Computers & Digital Techniques, 14(1), 27-36. doi:10.1049/iet-cdt.2019.0042DOI: 10.1049/iet-cdt.2019.0042
2019
Reddy, R. P., Acharyya, A., & Khursheed, S. (2019). A Framework for TSV based 3D-IC to Analyze Aging and TSV Thermo-mechanical stress on Soft Errors. In 2019 IEEE INTERNATIONAL TEST CONFERENCE IN ASIA (ITC-ASIA 2019) (pp. 121-126). doi:10.1109/ITC-Asia.2019.00034DOI: 10.1109/ITC-Asia.2019.00034
Miele, A., Trefzer, M. A., & Khursheed, S. (2019). Guest Editorial: Defect and Fault Tolerance in VLSI and Nanotechnology Systems. IET COMPUTERS AND DIGITAL TECHNIQUES, 13(3), 127-128. doi:10.1049/iet-cdt.2019.0097DOI: 10.1049/iet-cdt.2019.0097
Khursheed, S., & Rossi, D. (2019, July 1). Detection of Recycled ICs via On-Chip Leakage Current Sensors. In 4th International Verification and Security Workshop (IVSW). Rhodes Island, Greece.
Fault Tolerance in 3D-ICs (Chapter)
Reddy, R. P., Acharyya, A., & Khursheed, S. (2019). Fault Tolerance in 3D-ICs. In Internet of Things (pp. 155-178). Springer International Publishing. doi:10.1007/978-3-030-02807-7_8DOI: 10.1007/978-3-030-02807-7_8
2018
Foreword (Conference Paper)
Foreword (2018). In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE. doi:10.1109/dft.2018.8602980DOI: 10.1109/dft.2018.8602980
Rossi, D., Tenentes, V., Khursheed, S., & Reddy, S. (2018). Recycled IC Detection through Aging Sensor. In European Test Symposium.
Tenentes, V., Rossi, D., Khursheed, S. S., Al-Hashimi, B. M., & Chakrabarty, K. (2018). Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs.. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems, 37(4), 883-895. doi:10.1109/TCAD.2017.2729462DOI: 10.1109/TCAD.2017.2729462
2017
Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing (Journal article)
Sabbavarapu, S., Basireddy, K. R., Acharyya, A., & Khursheed, S. (2017). Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing. JOURNAL OF LOW POWER ELECTRONICS, 13(3), 456-471. doi:10.1166/jolpe.2017.1506DOI: 10.1166/jolpe.2017.1506
Reddy, R. P., Acharyya, A., & Khursheed, S. (2017). A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 25(7), 2071-2080. doi:10.1109/TVLSI.2017.2681703DOI: 10.1109/TVLSI.2017.2681703
Welcome message (Conference Paper)
Welcome message (2017). In 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE. doi:10.1109/dft.2017.8244425DOI: 10.1109/dft.2017.8244425
Tenentes, V., Rossi, D., Yang, S., Khursheed, S., Al-Hashimi, B. M., & Gunn, S. R. (2017). Coarse-grained Online Monitoring of BTI Aging by Reusing Power Gating Infrastructure. IEEE Transactions on Very Large Scale Integration Systems, 25(4), 1397-1407. doi:10.1109/TVLSI.2016.2626218DOI: 10.1109/TVLSI.2016.2626218
Rossi, D., Tenentes, V., Yang, S., Khursheed, S., & Al-Hashimi, B. M. (2017). Aging Benefits in Nanometer CMOS Designs. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 64(3), 324-328. doi:10.1109/TCSII.2016.2561206DOI: 10.1109/TCSII.2016.2561206
2016
Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs (Conference Paper)
Zhao, Y., Khursheed, S., Al-Hashimi, B. M., & Zhao, Z. (2016). Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs. In 2016 IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC). Retrieved from https://www.webofscience.com/
Khursheed, S. (2016). Reconfigurable hardware-software codesign methodology for protein identification. doi:10.1109/EMBC.2016.7591227DOI: 10.1109/EMBC.2016.7591227
Rossi, D., Tenentes, V., Yang, S., Khursheed, S., & Al-Hashimi, B. M. (2016). Reliable Power Gating With NBTI Aging Benefits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(8), 2735-2744. doi:10.1109/TVLSI.2016.2519385DOI: 10.1109/TVLSI.2016.2519385
Khursheed, S., Vivet, P., Hopsch, F., & Marinissen, E. J. (2016). Guest Editors' Introduction: Robust 3-D Stacked ICs. IEEE Design & Test, 33(3), 6-7. doi:10.1109/mdat.2016.2542210DOI: 10.1109/mdat.2016.2542210
Application-Specific Memory Protection Policies for Energy-Efficient Reliable Design (Conference Paper)
Yang, S., Shafik, R. A., Khursheed, S., Flynn, D., Merrett, G. V., & Al-Hashimi, B. M. (2015). Application-Specific Memory Protection Policies for Energy-Efficient Reliable Design. In 2015 INTERNATIONAL SYMPOSIUM ON RAPID SYSTEM PROTOTYPING (RSP) (pp. 18-24). Retrieved from https://www.webofscience.com/
2015
Tenentes, V., Khursheed, S., Rossi, D., Yang, S., & Al-Hashimi, B. M. (2015). DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 34(12), 2013-2024. doi:10.1109/TCAD.2015.2446939DOI: 10.1109/TCAD.2015.2446939
BTI and Leakage Aware Dynamic Voltage Scaling for Reliable Low Power Cache Memories (Conference Paper)
Rossi, D., Tenentes, V., Khursheed, S., & Al-Hashimi, B. M. (2015). BTI and Leakage Aware Dynamic Voltage Scaling for Reliable Low Power Cache Memories. In 2015 IEEE 21ST INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS) (pp. 194-199). Retrieved from https://www.webofscience.com/
Online Fault Tolerance Technique for TSV-Based 3-D-IC (Journal article)
Zhao, Y., Khursheed, S., & Al-Hashimi, B. M. (2015). Online Fault Tolerance Technique for TSV-Based 3-D-IC. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 23(8), 1567-1571. doi:10.1109/TVLSI.2014.2343156DOI: 10.1109/TVLSI.2014.2343156
Diagnosis of Power Switches with Power-Distribution-Network Consideration (Conference Paper)
Tenentes, V., Rossi, D., Khursheed, S., & Al-Hashimi, B. M. (2015). Diagnosis of Power Switches with Power-Distribution-Network Consideration. In 2015 20th IEEE European Test Symposium (ETS). Retrieved from https://www.webofscience.com/
NBTI and Leakage Aware Sleep Transistor Design for Reliable and Energy Efficient Power Gating (Conference Paper)
Rossi, D., Tenentes, V., Khursheed, S., & Al-Hashimi, B. M. (2015). NBTI and Leakage Aware Sleep Transistor Design for Reliable and Energy Efficient Power Gating. In 2015 20TH IEEE EUROPEAN TEST SYMPOSIUM (ETS). Retrieved from https://www.webofscience.com/
2014
High Quality Testing of Grid Style Power Gating (Conference Paper)
Tenentes, V., Khursheed, S., Al-Hashimi, B. M., Zhong, S., & Yang, S. (2014). High Quality Testing of Grid Style Power Gating. In 2014 IEEE 23RD ASIAN TEST SYMPOSIUM (ATS) (pp. 186-191). doi:10.1109/ATS.2014.37DOI: 10.1109/ATS.2014.37
Khursheed, S., Shi, K., Al-Hashimi, B. M., Wilson, P. R., & Chakrabarty, K. (2014). Delay Test for Diagnosis of Power Switches. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 22(2), 197-206. doi:10.1109/TVLSI.2013.2239319DOI: 10.1109/TVLSI.2013.2239319
Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive Open and Bridge Defects (Journal article)
Zhong, S., Khursheed, S., Al-Hashimi, B. M., & Zhao, W. (2014). Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive Open and Bridge Defects. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 33(5), 798-810. doi:10.1109/TCAD.2013.2295812DOI: 10.1109/TCAD.2013.2295812
2013
Impact of PVT variation on Delay Test of Resistive Open and Resistive Bridge Defects (Conference Paper)
Thong, S., Khursheed, S., & Al-Hashimi, B. M. (2013). Impact of PVT variation on Delay Test of Resistive Open and Resistive Bridge Defects. In PROCEEDINGS OF THE 2013 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS) (pp. 230-235). Retrieved from https://www.webofscience.com/
Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation (Journal article)
Yang, S., Khursheed, S., Al-Hashimi, B. M., Flynn, D., & Merrett, G. V. (2013). Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 60(11), 2953-2961. doi:10.1109/TCSI.2013.2252640DOI: 10.1109/TCSI.2013.2252640
2011
Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation (Conference Paper)
Zhong, S., Khursheed, S., Al-Hashimi, B. M., Reddy, S. M., & Chakrabarty, K. (2011). Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation. In 2011 20TH ASIAN TEST SYMPOSIUM (ATS) (pp. 389-394). doi:10.1109/ATS.2011.16DOI: 10.1109/ATS.2011.16
Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs (Conference Paper)
Zhao, Y., Khursheed, S., & Al-Hashimi, B. M. (2011). Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs. In 2011 20TH ASIAN TEST SYMPOSIUM (ATS) (pp. 201-206). doi:10.1109/ATS.2011.37DOI: 10.1109/ATS.2011.37
Yang, S., Khursheed, S., Al-Hashimi, B. M., Flynn, D., & Idgunji, S. (2011). Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 30(12), 1773-1785. doi:10.1109/TCAD.2011.2166590DOI: 10.1109/TCAD.2011.2166590
Zhong, S., Khursheed, S., & Al-Hashimi, B. M. (2011). A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 30(11), 1719-1730. doi:10.1109/TCAD.2011.2162065DOI: 10.1109/TCAD.2011.2162065
Improved DFT for Testing Power Switches (Conference Paper)
Khursheed, S., Yang, S., Al-Hashimi, B. M., Huang, X., & Flynn, D. (2011). Improved DFT for Testing Power Switches. In 2011 16TH IEEE EUROPEAN TEST SYMPOSIUM (ETS) (pp. 7-12). doi:10.1109/ETS.2011.63DOI: 10.1109/ETS.2011.63
2010
Test Strategies for Multivoltage Designs (Chapter)
Khursheed, S., & Al-Hashimi, B. M. (2010). Test Strategies for Multivoltage Designs. In POWER-AWARE TESTING AND TEST STRATEGIES FOR LOW POWER DEVICES (pp. 243-271). doi:10.1007/978-1-4419-0928-2_8DOI: 10.1007/978-1-4419-0928-2_8
Khursheed, S., Al-Hashimi, B. M., Chakrabarty, K., & Harrod, P. (2010). Gate-Sizing-Based Single V<sub>dd</sub> Test for Bridge Defects in Multivoltage Designs. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 29(9), 1409-1421. doi:10.1109/TCAD.2010.2059310DOI: 10.1109/TCAD.2010.2059310
Scan Based Methodology for Reliable State Retention Power Gating Designs (Conference Paper)
Yang, S., Al-Hashimi, B. M., Flynn, D., & Khursheed, S. (2010). Scan Based Methodology for Reliable State Retention Power Gating Designs. In 2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010) (pp. 69-74). Retrieved from https://www.webofscience.com/
Modeling the Impact of Process Variation on Resistive Bridge Defects (Conference Paper)
Khursheed, S., Zhong, S., Al-Hashimi, B. M., Aitken, R., & Kundu, S. (2010). Modeling the Impact of Process Variation on Resistive Bridge Defects. In INTERNATIONAL TEST CONFERENCE 2010. Retrieved from https://www.webofscience.com/
2009
Khursheed, S., Al-Hashimi, B. M., Reddy, S. M., & Harrod, P. (2009). Diagnosis of Multiple-Voltage Design With Bridge Defect. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 28(3), 406-416. doi:10.1109/TCAD.2009.2013540DOI: 10.1109/TCAD.2009.2013540
Ingelsson, U., Al-Hashimi, B. M., Khursheed, S., Reddy, S. M., & Harrod, P. (2009). Process Variation-Aware Test for Resistive Bridges. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 28(8), 1269-1274. doi:10.1109/TCAD.2009.2021728DOI: 10.1109/TCAD.2009.2021728
Test Cost Reduction for Multiple-Voltage Designs with Bridge Defects through Gate-Sizing (Conference Paper)
Khursheed, S., Al-Hashimi, B. M., & Harrod, P. (2009). Test Cost Reduction for Multiple-Voltage Designs with Bridge Defects through Gate-Sizing. In DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3 (pp. 1349-+). Retrieved from https://www.webofscience.com/
2008
Bridge defect diagnosis for multiple-voltage design (Conference Paper)
Khursheed, S., Rosinger, P., Al-Hashimi, B. M., Reddy, S. M., & Harrod, P. (2008). Bridge defect diagnosis for multiple-voltage design. In PROCEEDINGS OF THE 13TH IEEE EUROPEAN TEST SYMPOSIUM: ETS 2008 (pp. 99-+). doi:10.1109/ETS.2008.14DOI: 10.1109/ETS.2008.14
Bridging fault test method with adaptive, power management awareness (Journal article)
Khursheed, S., Ingelsson, U., Rosinger, P., Al-Hashimi, B. M., & Harrod, P. (2008). Bridging fault test method with adaptive, power management awareness. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 27(6), 1117-1127. doi:10.1109/TCAD.2008.923247DOI: 10.1109/TCAD.2008.923247
2007
Resistive bridging faults DFT with adaptive power management awareness (Conference Paper)
Ingelsson, U., Rosinger, P., Khursheed, S. S., Al-Hashimi, B. M., & Harrod, P. (2007). Resistive bridging faults DFT with adaptive power management awareness. In PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM (pp. 101-+). doi:10.1109/ATS.2007.69DOI: 10.1109/ATS.2007.69
El-Maleh, A., & Khursheed, S. (2007). Efficient test compaction for combinational circuits based on Fault detection count-directed clustering. IET COMPUTERS AND DIGITAL TECHNIQUES, 1(4), 364-368. doi:10.1049/iet-cdt:20070004DOI: 10.1049/iet-cdt:20070004
2006
El-Maleh, A. H., Khursheed, S. S., & Sait, S. M. (2006). Efficient static compaction techniques for sequential circuits based on reverse-order restoration and test relaxation. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 25(11), 2556-2564. doi:10.1109/TCAD.2006.873895DOI: 10.1109/TCAD.2006.873895
2005
Efficient static compaction techniques for sequential circuits based on Reverse Order Restoration and test relaxation (Conference Paper)
El-Maleh, A. H., Khursheed, S. S., & Sait, S. M. (2005). Efficient static compaction techniques for sequential circuits based on Reverse Order Restoration and test relaxation. In 14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS (pp. 378-385). doi:10.1109/ATS.2005.53DOI: 10.1109/ATS.2005.53
